Improvement On Rectification And Regulation Of Power Conditioning Circuit For RF Energy Harvesting

Power management is one of critical issues in most of integrated circuit (IC) applications as it determines the ability of a device to maintain its operating time. Power management system can be divided into two parts, energy harvesting and low dropout (LDO) voltage regulator circuits. Due to the increase of radio frequency (RF) sources around the globe, RF energy harvesting system which mainly composes of a rectifier becomes promising solution to power the low-powered electronic devices as it offers low power density and smaller size of energy converter make it easily to be integrated into a chip. The sensitivity, efficiency, and output voltage play an important role in the design of rectifier for energy harvesting. High efficiency conventional rectifiers typically provide either high sensitivity or high output voltage characteristics. Due to the limitation in rectifier architectures and the physical structure of transistor that causing large voltage drop across the rectifier over a wide range of sensitivity and output voltage, improving one of the characteristics trades off the other. The objective of this research is to design a high efficiency rectifier that operates at high sensitivity, targeting urban and rural areas and producing large output voltage that is sufficient to supply low-power electronic devices. The proposed rectifier comprises bulk-to-source BTMOS differential-drive based rectifier to produce a high efficiency RF energy harvesting system. Low-pass upward matching network is applied at the rectifier input to minimize the power loss between antenna and the rectifier hence increasing the sensitivity and output voltage. Dual-oxide-thickness transistors are used in the rectifier circuit to optimize the power efficiency at each of the rectifier’s stage over a wide range of output voltage and sensitivity. The system is designed using 0.18μm Silterra RF in deep n-well process technology and produces 3.997V output at -15dBm sensitivity without the need of complex auxiliary control circuit and DC – DC charge-pump circuit. Meanwhile, technology scaling in modern IC industries causing the ripple noise from power supply become dominant for analogue and RF circuits. RF circuit demands for voltage regulator that has high power supply rejection ratio (PSRR) and low temperature coefficient as this circuit is very sensitive to noise. Small changes in its supply voltage may cause the circuit not functioning properly. Conventional regulators provide high PSRR, but it typically focuses on low frequency application. Due to this reason, LDO with high PSRR at high frequency and low temperature coefficient over a wide range of temperature is proposed. The proposed LDO uses rail-to-rail folded cascode amplifier to achieve high PSRR while obtaining good open-loop gain and stability. Large 1μF off-chip load capacitor is used to further increase the PSRR. The LDO uses transistors operating in weak and strong inversions at the voltage reference circuit to achieve 2nd order voltage-temperature characteristic hence reducing the temperature coefficient. The LDO is designed using 0.18μm Silterra thick-oxide technology and produces a constant 1.8V output voltage for input voltage between 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The LDO achieves more than 100dB PSRR for frequency greater than 900MHz and obtained temperature coefficient of lower than 5ppm/°C within the desired temperature range

128 mA CMOS LDO with 108 db PSRR at 2.4 MHz frequency

A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1µF off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC. The characteristic is achieved by implementing MOSFET transistors operate in weak and strong inversions. The LDO is designed using 0.18µm CMOS technology and achieves a constant 1.8V output voltage for input voltages from 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The proposed LDO is targeted for RF application which has stringent requirement on noise rejection over a broad range of frequency

3.3V DC Output At-16dBm Sensitivity And 77% PCE Rectifier For RF Energy Harvesting

This paper presents a high voltage conversion at high sensitivity RF energy harvesting system for IoT applications. The harvesting system comprises bulk-to-source (BTMOS) differential-drive based rectifier to produce a high efficiency RF energy harvesting system. Low-pass upward impedance matching network is applied at the rectifier input to increase the sensitivity and output voltage. Dual-oxide-thickness transistors are used in the rectifier circuit to maintain the power efficiency at each stage of the rectifier. The system is designed using 0.18μm Silterra RF in deep n-well process technology and achieves 4.07V output at -16dBm sensitivity without the need of complex auxiliary control circuit and DC-DC charge-pump circuit. The system is targeted for urban environment

-31 DBM Sensitivity High Efficiency Rectifier For Energy Scavenging

RF energy scavenging is capable in converting RF signals into electricity and has become a promising solution to power energy-constrained wireless networks.However,it has low power conversion efficiency especially when the harvested RF power is small.For this reason,we propose an enhanced differential-drive rectifier to improve the efficiency and the sensitivity of rectifier for energy scavenging applications.The proposed rectifier achieves dynamically controlled threshold voltage and reduces leakage current in the transistors through DTMOS transistor in differential-drive topology.The voltage boosting circuit further increases the sensitivity through step up the input signal before the signal enters the rectifier.The decoupling capacitor shunts the noise of the input signal before the signal is injected into the cross-connected gate reducing the voltage drop and maintaining the PCE of the rectifier.The rectifier is designed based on the 0.18 µm Silterra CMOS process technology.Effects of decoupling capacitors,voltage boosting circuit and output load on PCE of the rectifier have been evaluated.Technology scaling and parasitic effects to the rectifier have also been presented. Performance of N-stages proposed rectifier has been compared with the conventional BTMOS rectifier.The proposed method achieves the highest sensitivity of −31 dBm for 1, 3 and 5 stages rectifiers without the need of off-chip load capacitor